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D atasheet Version 2.0, Decem ber 2006
ICE2QS01 Quasi-resonant C o n troller PWM
Power Management & Supply
Never
stop
thinking.
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ICE2QS01 Revision History: Previous Version: Page Subjects (major changes since last revision) 11 December 2006 Datasheet
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Edition 11 December 2006 Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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ICE2QS01
Quasi-Resonant PWM Controller
Product Highlights
* Active burst mode for low standby power * Digital frequency reduction for better overall system efficiency * Integrated power cell for IC self-power supply
ICE2QS01
PG-DIP-8
Features
* * * * * * * * * * * Quasiresonant operation till very low load Active burst mode operation at light load for low standby input power (< 1W) Digital frequency reduction with decreasing load Power cell for VCC pre-charging and IC power supply during latch-off, or standby mode operation when it is necessary Built-in digital soft-start Foldback correction and cycle-by-cycle peak current limitation Auto restart mode for VCC Overvoltage protection Auto restart mode for VCC Undervoltage protection Auto restart mode for openloop/overload protection Latch-off mode for adjustable output overvoltage protection Latch-off mode for Short-winding protection
Description
ICE2QS01 is a quasi-resonant PWM controller optimized for off-line switch power supply applications such as LCD TV, CRT TV and notebook adapter. The digital frequency reduction with decreasing load enables a quasi-resonant operation till very low load. As a result, the system efficiency is significantly improved compared to other conventional solutions. The active burst mode operation enables an ultra-low power consumption at standby mode with small and controllable output voltage ripple. The innovative power cell solves the IC power supply problem when the output voltage is pulled down during standby mode, or during latch-off mode. The numerous protection functions give a full protection of the power supply system in failure situations. All of these make the ICE2QS01 an outstanding controller for quasiresonant flyback converter in the market.
Typical Application
Cbus 85 ~ 265 VAC CVCC Dr1~Dr4 HV Power Cell
Gate Driver
Snubber RVCC DVCC RZC2 RZC1 CZC DZC
Wp
Ws
DO CO
Lf
Cf
VO
Wa
VCC
ZC Q1 OUT
CPS Rb1 Rb2 Rc1 Rovs1
CDS
GND CREG
PWM Controller
Zero Crossing Detection Power Management Digital Process Block Active Burst Mode
Optocoupler
Current Limitation
CS RCS
REG
Protection Block Current Mode Control
ICE2QS01
TL431
Cc1
Cc2 Rovs2
Type ICE2QS01
Package PG-DIP-8
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Table of Contents Page 1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 Package PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 5 Representative Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 VCC Pre-Charging and Typical VCC Voltage During Start-up . . . . . . . . . . . .7 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Switch-on Determination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Switch-off Determination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Entering Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .10 During Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Leaving Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .10 IC Power Supply During Active Burst Moe Operation . . . . . . . . . . . . . . .10 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
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Pin Configuration and Functionality
1
1.1
Pin Configuration and Functionality
Pin Configuration
REG (Regulation) Normally, an external capacitor is connected to this pin for a smooth voltage Vreg. Internally, this pin is connected to the PWM signal generator for switch-off determination (together with the current sensing signal), the digital signal processing for the frequency reduction with decreasing load during normal operation, and the burst mode controller for entering burst mode operation determination and burst ratio control during burst mode operation. Additionally, the open-loop / over-load protection is implemented by monitoring the voltage at this pin. CS (Current Sensing) This pin is connected to the shunt resistor for the primary current sensing, externally, and the PWM signal generator for switch-off determination (together with the regulation voltage), internally. Moreover, shortwinding protection is realised by monitoring the voltage Vcs during on-time of the main power switch.
Pin 1 2 3 4, 5 6 7 8
Symbol ZC REG CS HV OUT VCC GND
Function Zero Crossing Regulation Primary Current Sensing High Voltage input gate driver output IC supply voltage Common ground
1.2
Package PG-DIP-8
ZC
1
8
GND
REG
2
7
VCC
CS
3
6
OUT
HV (High Voltage) The pin HV is connected to the bus voltage, externally, and to the power cell, internally. The current through this pin pre-charges the VCC capacitor once the supply bus voltage is applied. Additionally, the current through this pin supplies the IC in case that the output voltage is lowered during active burst mode operation, or during latch-off mode. OUT (Gate drive output) This output signal drives the external main power switch, which is a power MOSFET in most case. VCC (Power supply) This is the IC power supply pin. Externally, this pin is connected to the VCC capacitor, which is supplied by the inside power cell during VCC charge-up, burst mode operation at lowered output voltage or during latched-off of the IC, and the auxiliary winding during normal operation or burst mode operation with high enough voltage across the auxiliary winding. Based on this voltage, the VCC under- or over-voltage protection are implemented. GND (Ground) This is the common ground of the controller.
HV
4
5
HV
Figure 1
Pin Configuration PG-DIP-8(top view)
1.3
Pin Functionality
ZC (Zero Crossing) At this pin, the voltage from the auxiliary winding after a time delay circuit is applied. Internally, this pin is connected to the zero-crossing detector for switch-on determination. Additionally, the output overvoltage detection is realized by comparing the voltage Vzc with an internal preset threshold.
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Representative block diagram
2
Representative block diagram
VZCT2 VZCT1 ZC 1 VOLP OLP VCC OVP VCC UVP RReg
VREF
ringing suppression time control Zero-crossing counter up/down counter active burst control PWM generator on/off FF gate driver
VVCCOVP
auto restart
REG 2
Vvccuvp VOPOVP output OVP latch off
VcsSW
SWP
CS 3
current limitation / foldback correction Vcsth power management power cell controller current measurement v1
OUT 6
HV 4, 5 VCC 7
GND 8
Vos
Figure 2
Representative Blockdigram
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Quasi-Resonant PWM Controller ICE2QS01
Functional Description
3
3.1
Functional Description
VCC Pre-Charging and Typical VCC Voltage During Start-up
In the controller ICE2QS01, a power cell is integrated. As shown in Figure 2, the power cell consists of a high voltage device and a controller, whereby the high voltage device is controlled by the controller. The power cell provides a pre-charging of the VCC capacitor till VCC voltage reaches the VCC turned-on threshold VVCCon and the IC begins to operate, while it may keep the VCC voltage at a constant value during burst mode operation when the output voltage is pulled down or the power from the auxiliary winding is not enough, or when the IC is latched off in certain protection mode. Once the mains input voltage is applied, a rectified voltage shows across the capacitor Cbus. The high voltage device provides a current to charge the VCC capacitor Cvcc. Before the VCC voltage reaches a certain value, the amplitude of the current through the high voltage device is only determined by its channel resistance and can be as high as several mA. After the VCC voltage is high enough, the controller controls the high voltage device so that a constant current around 1mA is provided to charge the VCC capacitor further, until the VCC voltage exceeds the turned-on threshold VVCCon. As shown as the time phase I in Figure 3, the VCC voltage increase near linearly.
VCC VVCCon VVCCUVP i ii iii
drops (Phase II). Once the output voltage is high enough, the VCC capacitor receives then energy from the auxiliary winding from the time point t2 on. The VCC then will reach a constant value depending on output load. Since there is a VCC undervoltage protection, the capacitance of the VCC capacitor should be selected to be high enough to ensure that enough energy is stored in the VCC capacitor so that the VCC voltage will never touch the VCC under voltage protection threshold VVCCUVP before the output voltage is built up. Therefore, the capacitance should fulfill the following requirement: I VCCop ( t2 - t 1 ) C vcc ----------------------------------------------V VCCon - V VCCUVP with IVCCop the operating current of the controller. [2]
3.2
Soft-start
At the time t1, the IC begins to operate with a soft-start. By this soft-start the switching stresses for the switch, diode and transformer are minimised. The soft-start implemented in the ICE2QS01 is a digital time-based function. The preset soft-start time is 24ms with 8 steps. The internal reference for the regulation voltage begins at 1.35V and with an increment of 0.35V for each following step.
3.3
Normal Operation
t1
t2
t
Figure 3
VCC voltage at start up
The time taking for the VCC pre-charging can then be approximately calculated as: V VCCon C vcc t 1 = --------------------------------I VCCch arg e2 [1]
where IVCCcharge2 is the charging current from the power cell which is 1.05mA, typically. Exceeds the VCC voltage the turned-on threshold VVCCon of at time t1, the power cell is switched off, and the IC begins to operate with a soft-start. Due to power consumption of the IC and the fact that still no energy from the auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC voltage
The PWM section of the IC can be divided into two main portions: PWM controller for normal operation and PWM controller for burst mode operation. The PWM controller for normal operation will be described in the following paragraphs, while the PWM controller for burst mode operation will be discussed in the next section. The PWM controller for normal operation consists of digital signal processing circuit including an up/down counter, a zero-crossing counter (ZC-counter) and a comparator, and analog circuit including a current measurement unit and a comparator. The switch-on and -off time point is determined by the digital circuit and the analog circuit, respectively. As input information for the switch-on determination, the zerocrossing input signal and the value of the up/down counter are needed, while the feedback signal vREG and the current sensing signal vCS are necessary for the switch-off determination. Details about the operation of the PWM controller in normal operation are illustrated in the following paragraphs. 3.3.1 Switch-on Determination As mentioned above, the digital signal processing circuit consists of an up/down counter, a zero-crossing counter and a comparator. A ringing suppression time
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Functional Description
controller is implemented to avoid mistriggering by the ring after MOSFET is turned off. Functionality of these parts is described as in the following. 3.3.1.1 Up/down Counter The up/down counter stores the number of zero crossing to be ignored before the main power switch is switched on after demagnetisation of the transformer. This value is a function of the regulation voltage, which contains information about the output power. Generally, a high output power results in a high regulation voltage. According to this information, the value in the up/down counter is changed to a low value in case of high regulation voltage, and to a high value in case of low regulation voltage. In ICE2QS01, the lowest value of the counter is 1 and the highest 7. Following text explains how the up/down counter value changes in responding to the regulation voltage vREG. The regulation voltage vREG is internally compared with three thresholds VRL, VRH and VRM. According to the results, the value in the up/down counter is changed, which is summarised in Table 1 and Figure 4 respectively. Table 1 Operation of the up/down counter up/down counter vREG action Count upwards till Always lower than VRL 7 Stop counting, no Once higher than VRL, but always lower than VRH value changing Count downwards Once higher than VRH, but always lower than VRM till 1 Set up/down Once higher than VRM counter to 1
clock T=48ms
limited between 1 and 7. If the counter tends to count beyond this range, the attempt is ignored. In normal case, the up/down counter can only be changed by one each time at the clock period of 48ms. However, to ensure a fast response to sudden load increase, the counter is set to 1 in the following switching period after the regulation voltage vREG exceeds the threshold VRM. Zero-Crossing Counter and Ringing Suppression Time Controller In the system, the voltage from the auxiliary winding is applied to the zero-crossing pin through a RC network, which provides a time delay to the voltage from the auxiliary winding. Internally, this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage (OP OVP) detector and a ringing suppression time controller. During on-state of the power switch a negative voltage applies to the ZC pin. Through the internal clamping network, the voltage at the pin is clamped to certain level. However, it is highly recommended that a fastrecovery diode Dzc is added to block the negative voltage when the power switch is on. This is because the device in MOS technology is sensitive to negative voltage. The voltage at the ZC pin vZC is compared with the threshold VZCT1. Once the voltage vZC crosses the threshold at its falling edge, a pulse is generated which is fed to the zero-crossing counter and the counter value increases by 1. After MOSFET is turned on, there will be some oscillation on VDS, which will also appear on the voltage on ZC pin. To avoid the MOSFET is turned on mistriggerred by such oscillation, a ringing suppression timer is implemented. The time is dependent on the voltage vZC. When the voltage vZC is lower than the threshold VZCT2, a longer preset time applies, while a shorter time is set when the voltage vZC is higher than the threshold. The voltage vZC is used for the output overvoltage protection, as well. Once the voltage at this pin is higher than the threshold VOPOVP during off-time of the main switch, the IC is latched off after a fixed blanking time. To achieve the switch-on at voltage valley, the voltage from the auxiliary winding is fed to a time delay network (the RC network consists of Dzc, Rzc1, Rzc2 and Czc as shown in typical application circuit) before it is applied to the zero-crossing detector through the ZC pin. The needed time delay to the main oscillation signal t should be approximately one fourth of the oscillation period (by transformer primary inductor and drainsource capacitor) minus the propagation delay from the 3.3.1.2
V FB V RM V RH V RL
t
t n+1 n+2 n+2 n+2 n+2 n+1 n-1 3 1 4 1 1 1 1 n Case 1 Case 2 Case 3 4 2 7 5 3 7 6 4 7 6 4 7 6 4 7 6 4 7 5 3 6 n 4 2 5
Figure 4
Up/down counter operation
According to the comparison results the up/down counter counts upwards, keeps unchanged or counts downwards. However, the value in up/down counter is
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Functional Description
detected zero-crossing to the switch-on of the main switch tdelay, theoretically: T osc t = --------- - t delay 4 [3] 3.3.2 Switch-off Determination In the converter system, the primary current is sensed by an external shunt resistor, which is connected between low-side terminal of the main power switch and the common ground. The sensed voltage across the shunt resistor vCS is applied to an internal current measurement unit, and its output voltage v1 is compared with the regulation voltage vreg. Once the voltage v1 exceeds the voltage vREG, the output flip-flop is reset. As a result, the main power switch is switched off. The relationship between the v1 and the vcs is described by: v 1 = 3.3 v CS + 0.7 [5]
This time delay should be matched by adjusting the time constant of the RC network which is calculated as: R zc1 R zc2 td = C zc --------------------------R zc1 + R zc2 [4]
3.3.1.3 Switch-on Determination In the system, turn-on of the power switch depends on the value of the up/down counter, the value of the zerocrossing counter and the voltage at the ZC pin vZC. Turn-on happens only when the value in the both counters are the same and the voltage at the ZC is lower than the threshold VZCT1. For comparison of the values from both counters, a digital comparator is used. Once these counters have the same value, the comparator generates a signal which sets the on/off flip-flop, only when the voltage vZC is lower than the threshold VZCT1. Another signal which may trigger the digital comparator is the output of a TsMax clock signal, which limits the maximum off time to avoid the low-frequency operation. During active burst mode operation, the digital comparator is disabled and no pulse will be generated.
1
To avoid mistriggering caused by the voltage spike across the shunt resistor after switch-on of the main power switch, a 330ns leading edge blanking time applies to output of the comparator. 3.3.3 Foldback Point Correction In addition to the cycle-by-cylce primary current limitation, the IC incorporats a foldback point correction. The current limit on CS pin voltage is now a time dependent one. If the mains input voltage is high, the MOSFET on time will be short and the current limit will be low. In such a way, the maximum output power for the SMPS designed with ICE2QS01 will be nearly constant against the variations of mains input voltage. The current sense voltage limit versus the MOSFET maximum on time is shown in Figure 5.
0 .8
Vcs-max(V)
0 .6
0 .4
0 .2
0 0 5 10 15 20 25 30
Ton(us)
Figure 5 Maximum current limit versus MOSFET maximum on time
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Functional Description 3.4 Active Burst Mode Operation
exceed VLB (4.5V). After leaving active busrt mode, maximum current can now be provided to stabilize VO. In addition, the up/down counter will be set to 1 immediately after leaving active burst mode. This is helpful to decrease the output voltage undershoot. IC Power Supply During Active Burst Mode During active burst mode operation, the power cell is activated again. Once the power from the auxiliary winding is not high enough to keep the VCC voltage above the preset value of VVCCBL, the power cell keeps the VCC voltage at the preset value VVCCBL. Otherwise, if the VCC voltage is still above this value, no current flows through the power cell though it is activated. 3.4.4
At very low load condition, the IC enters active burst mode operation to minimize the input power. Details about active burst mode operation are explained in the following paragraphs. 3.4.1 Entering Active Burst Mode Operation For determination of entering active burst mode operation, three conditions apply: the regulation voltage is lower than the threshold of VEB(1.1V). Accordingly, the peak voltage across the shunt resistor is 0.11V; the up/down counter has its maximal value of 7; and a certain blanking time (24ms). Once all of these conditions are fulfilled, the active burst mode flip-flop is set and the controller enters burst mode operation. This multi-conditional determination for entering active burst mode operation prevents mistriggering of entering active burst mode operation, so that the controller enters active burst mode operation only when the output power is really low during the preset blanking time. 3.4.2 During Active Burst Mode Operation After entering the Active Burst Mode the regulation voltage rises as VOUT starts to decrease due to the inactive PWM section. One comparator observes the regulation signal if the voltage level VBH (3.6V) is exceeded. In that case the internal circuit is again activated by the internal bias to start with swtiching. Turn-on of the power MOSFET is triggered by the timer. The PWM generator for burst mode operation composes of a timer with a fixed frequency of 80kHz, typically, and an analog comparator. Turn-off is resulted by comparison of the voltage signal v1 with an internal threshold, by which the voltage across the shunt resistor VcsB is 0.25V, accordingly. A turn-off can also be triggered by the maximal duty ratio controller which sets the maximal duty ratio to 50%. In operation, the output flip-flop will be reset by one of these signals which come first. If the output load is still low, the regulation signal decreases as the PWM section is operating. When regulation signal reaches the low threshold VBL(3.0V), the internal bias is reset again and the PWM section is disabled until next time regultaion siganl increases beyond the VBH threshold. If working in active burst mode the regulation signal is changing like a saw tooth between 3.0V and 3.6V shown in Figure 6. 3.4.3 Leaving Active Burst Mode The regulation voltage immediately increases if there is a high load jump. This is observed by one comparator. As the current limit is 25% during active burst mode a certain load is needed so that regulation voltage can
VREG
4.4V 3.6V 3.0V 1.1V
Entering Active Burst Mode
Leaving Active Burst Mode
Blanking Window (24ms)
VCS
1.0V 0.25V Current limit level during Active Burst Mode
t
VVCC
t
12.5V
VO
Max. Ripple < 1%
t
t
Figure 6 Signals in active burst mode
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Quasi-Resonant PWM Controller ICE2QS01
Functional Description 3.5 Protection Functions
The IC provides full protection functions. The following table summarizes these protection functions. Table 2 Protection features VCC Overvoltage VCC Undervoltage Overload/Open Loop Output Overvoltage Short Winding Auto Restart Mode Auto Restart Mode Auto Restart Mode Latched Off Mode Latched Off Mode
During operation, the VCC voltage is continuously monitored. In case of an under- or an over-voltage, the IC is reset and the main power switch is then kept off. After the VCC voltage falls below the threshold VVCCUVP, the power cell is activated. The VCC capacitor is then charged up. Once the voltage exceeds the threshold VVCCon, the IC begins to operate with a new soft-start. In case of open control loop or output over load, the regulation voltage will be pulled up . After a blanking time of 24ms, the IC enters auto-restart mode. The blanking time here enables the converter to provide a high power in case the increase in VREG is due to a sudden load increase. During off-time of the power switch, the voltage at the zero-crossing pin is monitored for output over-voltage detection. If the voltage is higher than the preset threshold vOPOVP, the IC is latched off after the preset blanking time. If the voltage at the current sensing pin is higher than the preset threshold vcsSW during on-time of the power switch, the IC is latched off. This is short-winding protection. During latch-off protection mode, the power cell is activated and it keeps the VCC voltage at the level of VVCCBL.
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Symbol VHV VVCC VREG VZC VCS VOUT Tj TS RthJA VESD -0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 Limit Values min. max. 500 27 5.0 5.0 5.0 27 125 150 90 2 V V V V V V C C K/W kV PG-DIP-8 Human body model1) Unit Remarks
Parameter HV Voltage VCC Supply Voltage REG Voltage ZC Voltage CS Voltage OUT Voltage Junction Temperature Storage Temperature Thermal Resistance Junction-Ambient ESD Capability
1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description. Symbol VVCC TjCon Limit Values min. max. 125 C Unit Remarks
Parameter VCC Supply Voltage Junction Temperature
VVCCUVP VVCCOVP V -25
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Electrical Characteristics 4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from - 25 oC to 125oC. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed. Symbol min. IVCCstart IVCCcharge1 IVCCcharge2 IVCCcharge3 0.55 1.05 0.88 0.2 2.5 300 Limit Values typ. 300 max. 550 5.0 1.60 50 3.6 A mA mA mA A mA A VVCC = 21V VVCC = 0V VVCC = 1V VVCC = 21V VHV= 610V at Tj = 100C Output low Unit Test Condition
Parameter Start-Up Current VCC Charge Current
Leakage Current of Power Cell Supply Current in normal operation Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Latch-off Mode Supply Current in Burst Mode with Inactive Gate Supply Voltage with no power from auxiliary winding in burst mode or in latch-off mode VCC Turn-On Threshold Internal Reference Voltage
IStartLeak IVCCop IVCCrestart
IVCClatch IVCCburst VVCCBL
-
300 500 12.5
950 -
A A V VREG = 2.5V VHV = 100V
VVCCon VREF
21.2 4.8
22.0 5.0
22.8 5.2
V V measured at pin REG, IREG = 0
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Electrical Characteristics
4.3.2 Parameter Regulation Pull-Up Resistor PWM-OP Gain Offset for Voltage Ramp Soft-Start time Ringing suppression threshold Minimum ringing suppression time Maximum ringing suppression time Threshold to set Up/Down Counter to one Threshold for downward counting Threshold for upward counting Counter time
1)
PWM Section Symbol min. RREG AV VOS tSOFTS VZCT2 tZCRST1 tZCRST2 VRM VRH VRL tCOUNT tsMax tLEB Vcsth VEB VLB VBH VBL fsB DmaxB VcsB 0.22 64 33 200 0.95 2.2 14 3.18 0.63 18 20 Limit Values typ. 23 3.3 0.7 21 50 0.7 4.2 42 3.9 3.2 2.5 48 42 330 1.0 1.1 4.5 3.6 3.0 80 0.5 0.25 0.3 V 96 60 460 1.05 5.5 max. 33 38 110 k V ms mV V s s V V V ms s ns V V V V V kHz VZC VZCT2 VZC < VZCT2 Unit Test Condition
Zero crossing threshold voltage VZCT1
Maximum restart time in normal operation Leading Edge Blanking Peak current limitation in normal operation Regulation voltage for entering Burst Mode Regulation voltage for leaving Burst Mode Regulation voltage for burst-on Regulation voltage for burst-off Fixed Switching Frequency in Burst Mode Max. Duty Cycle in Burst Mode Peak Current Limitation in Burst Mode
1) The parameter is not subject to production test - verified by design/characterization
Version 2.0
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December 2006
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Quasi-Resonant PWM Controller ICE2QS01
Electrical Characteristics
4.3.3 Parameter VCC overvoltage threshold VCC undervoltage threshold Over Load or Open Loop Detection threshold for OLP protection at REG pin Over Load or Open Loop Protection Blanking Time Output Overvoltage detection threshold at the ZC pin Threshold for short winding protection Note: 4.3.4 Parameter Output voltage at logic low Output voltage at logic high Protection Symbol min. VVCCOVP VVCCUVP VOLP 24 10.3 Limit Values typ. 25.0 11.0 4.5 max. 26 11.7 V V V Unit Test Condition
TOLP-B VOPOVP VcsSW
16
24 4.5 1.68
35
ms V V
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP Gate Driver Symbol min. VGATElow VGATEhigh Limit Values typ. 0.7 10.0 1.0 100 25 max. V V V V ns ns IOUT = 20mA IOUT = -20mA VVCC = 7V IOUT = 20mA COUT = 4.7nF COUT = 4.7nF Unit Test Condition
Output voltage active shut down VGATEasd Rise Time Fall Time trise tfall
Version 2.0
15
November 2006
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Quasi-Resonant PWM Controller ICE2QS01
Outline Dimension
5
Outline Dimension
PG-DIP-8 (Leadfree Plastic Dual In-Line Outline)
Figure 7 PG-DIP-8 *Dimensions in mm
Version 2.0
16
December 2006
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Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
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Published by Infineon Technologies AG

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